1. Field of the Invention
The present invention relates to a resizing process and an enlargement process of an inputted image signal, and more specifically, to an image processing circuit and an image processing method for resizing an inputted image signal in conformity to an output destination device (changing the image size) and performing enlarged display.
2. Description of Related Art
The operation of the conventional image processing circuit for resizing image data inputted from an image sensor etc. (performing a process of altering the size of image data in such a way as to fit a device at its destination) and outputting it that is disclosed in Japanese unexamined patent publication No. H10(1998)-171440 will be described using FIG. 7 and FIG. 8 (FIG. 1 and FIG. 2 in that Patent Publication of the prior art). An image display device 108 in FIG. 7 recognizes the head of a horizontal scanning line by an “L” period of a horizontal-synchronization-signal 138 using a rising edge of a clock signal 140 as a reference, and displays image data 135 in an “H” period of an enable signal 139. Suppose the horizontal scanning lines of the image data 135 inputted into the image display device 108 in FIG. 7 are y-lines, and a reduction ratio 131 of the image inputted into a gate-signal generating circuit 106 is y′/y (y′: integer). First, as a first operation in an arbitrary frame image, non-consecutive (y′-y)-lines of the horizontal synchronization signals are selected out of y-lines of the horizontal synchronization signals that constitute the image data 135, and designated as a processing line group.
Consider that one selected horizontal scanning line in the processing line group is a horizontal synchronization signal x in FIG. 8. The gate-signal generating circuit 106 generates a horizontal synchronization signal x corresponding to the horizontal scanning line x, an enable signal x, and a gate signal 137A used for performing a thinning-out process on a clock signal group x in a period of the horizontal scanning line x. A gate circuit 107 performs a thinning-out process on control signals of a horizontal synchronization signal 132, an enable signal 133, and a clock signal 134, respectively, and generates a horizontal synchronization signal 138A, an enable signal 139A, and a clock signal 140A.
At this time, the processing line group except the horizontal scanning line x is also subjected to the thinning-out process similarly, that is, the horizontal synchronization signal 132, an enable signal 133, and the clock signal 134 that correspond to the horizontal synchronization signal x are thinned out in the gate circuit 107. The image display device 108 displays the image using the horizontal synchronization signal 138A, the enable signal 139A, the clock signal 140A, and a vertical synchronization signal 130 that are all generated by the above procedure as well as the inputted image data 135. At this time, apart of the image data 135 consisting of the horizontal scanning lines selected as the processing line group is not displayed on the image display device 108 because corresponding control signals have been thinned out in the gate circuit 107. As a result, an image that has been reduced by a reduction ratio y′/y in the vertical direction and hence consists of y′-lines of the horizontal scanning lines will be displayed on the image display device 108.
The operation of another conventional image processing circuit for enlarging image data disclosed in Japanese unexamined patent publication No. S61(1986)-227477 will be described using FIG. 9 through FIG. 11. A pixel clock CK201 from a timing control unit 223 (FIG. 9) is periodically given, as shown in FIG. 11A. An address counter 231 (FIG. 10) counts this pixel clock CK201, and outputs an address signal that increases or decreases by one for each pulse cyclically for every m-pulses of the pixel clock CK201. A clock memory 233 uses this output as its address input, and outputs sequentially the above-mentioned data (FIG. 11B) currently stored at that address. An AND circuit 234 received this data gates the pixel clock CK201 by this data, and generates a clock CK203 in the form such that pulses of the pixel clock CK201 are deleted regularly as shown in FIG. 11C. An address counter 236 generates an address output (FIG. 11D) corresponding to the periodic pixel clock CK201 and gives it to an image memory device 218. Therefore, when writing the image data, original pixel data inputted into this circuit, as it is, is stored in the image memory device 218.
Next, consider a reading operation in the case of enlargement. In doing this, the operation differs from the above-mentioned writing operation in the following points. That is, a selector 235 (FIG. 10) select B input, i.e., a clock CK203. Then, a pulse in the form of FIG. 11C will be given to the address counter 236. As shown in FIG. 11E, at a location where the pulse of the clock CK203 is lost, the same address will be accessed successively. Because of this, reading the image data from the image memory device 218 will be done in such a way that a pixel having the identical content is given two or more times successively in these locations and the next pixel is read out, resulting in an enlarged reproduction of the image.